The use of programmable array logic (PAL) devices to implement logic functions is well known in the art. External programming equipment programs the PAL with a fuse map representing the desired logic functions. Upon completion of programming, the external programming equipment verifies the storage integrity of the PAL by inputting known data (test vectors) and testing the resulting output. If the resulting output is the anticipated output, the stored fuse map is assumed to be accurate.
The storage integrity of a PAL that stores a fuse map representing a security sensitive encryption algorithm must be completely verified immediately after programming and prior to execution. To completely verify the storage integrity of a PAL, test vectors have at least two problems. First, a test vector needs to be generated for each input combination, thus a long test cycle is required. (For a 16-input PAL, the external programming equipment would have to generate 2.sup.16 (65,536) test vectors for each output.) Second, during normal in-field operation, the external programming equipment is usually not available, making the storage integrity of the PAL difficult to test. If the test vectors are stored with in the same circuitry as the PAL is employed, security sensitive information could be inferred from the storage of the test vectors.
Therefore, a need exists for a PAL verification system which can reasonably and completely verify the stored fuse map during programming, after completion of programming and prior to execution without revealing security sensitive information.